1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits and more particularly, to a semiconductor integrated circuit having a CPU and peripheral circuits (resources) built therein and also having a debugging support unit.
2. Description of the Related Art
FIG. 1 is a block circuit diagram showing major parts of a semiconductor integrated circuit 1 (chip) in the prior art. The semiconductor integrated circuit 1 includes a CPU (Central Processing Unit) 2 which executes instructions, a resource 3 such as a RAM (Random Access Memory) and a timer and so forth, and a bus controller 4. The semiconductor integrated circuit 1 further includes a debugging support unit (DSU) 5, an address bus 6 and a data bus 7. The CPU 2 outputs instruction addresses to the debugging support unit 5, which outputs the instruction addresses to a debugging tool 10. The semiconductor integrated circuit 1 further includes a control signal line or instruction address bus 8, through which read/write signals, wait signals and so forth are supplied from the CPU 2 to the debug tool 10 via the DSU 5. The bus controller communicates with external devices (not shown) through an external bus 9. This chip (semiconductor integrated circuit) 1 is connected with the debugging tool 10, which monitors all the operation performed by the CPU 2 and can stop the operation of the CPU 2 when a running program branches out to an address which does not exists.
Recently, the operation frequency inside the CPU has been greatly increased, and the operation frequency on a tool bus 11 comes to be unable to catch up with the CPU operation. Further, as it becomes difficult to adjust skew between bits when the operation becomes of a higher rate, it becomes difficult to prepare a bit width same as the bit width of the internal bus of the CPU 2.
In order to compensate the difference in ability between the CPU bus and tool bus 11, trace data has been once stored in a buffer memory (FIFO), adjusted so as to match with the frequency and bit width of the tool bus 11 and then outputted onto the tool bus 11 in the prior art. Thereby, the trace data is outputted to the tool bus 11 with a delay from the real timing at which the CPU executes instructions. Furthermore, in the prior art, after the CPU detects a break request from the debugging tool 10, the CPU outputs all the data stored in the buffer memory (FIFO), and then break processing is at last started.
Thereby, a useless time duration occurs, from the time the break request is detected until the break processing is actually started, in which neither a user program for performing the actual operation of the system nor an emulator program performing debugging of the system is executed. Accordingly, especially in such a system as that of mechanical controlling in which real-time operation of program is important, breaking processing such as re-writing memory contents while emulating the actual operation cannot be performed.
Therefore, in a case of such breaking processing as that for which a debugging person does not have to examine trace data, it is necessary to shorten the time duration from the CPU break until the emulator program processing is started so that the suspended period during which the execution of the user program is stopped by the break processing should be limited so as not to adversely affect the real-time execution.